Recently, it has become significantly difficult to reduce the size of an integrated circuit in accordance with the scaling rule. As one of the reasons, it has been difficult to restrain short-channel effect in a MOS (Metal-Oxide-Semiconductor) type FET (Field Effect Transistor) as an elementary element in an integrated circuit. For solving this problem, there has been proposed an FET having a double gate structure (Non-patent reference 1: Applied Physics, the Japan Society of Applied Physics, 2003, Vol. 72 (9), pp 1136-1142). A double-gate structure FET may have three configurations depending on arrangement of a source electrode, a drain electrode and two gate electrodes as described in Non-patent reference 1, and among these, FinFET (Fin-type channel FET) is believed to be practically used because an existing integrated circuit process may be easily applied to it.
FIG. 29 schematically shows a common FinFET as described in Non-patent reference 1. The FinFET is formed in an SOI (Silicon on Insulator) layer on a Si substrate 1 and a buried oxide film 2. The SOI layer has pads for a source electrode 3 and for a drain electrode 4, which are connected via a fin 5. There is formed a hard mask 9 in the upper surface of the fin 5 under a gate electrode 6 and there is formed a gate insulating film 7 between the side surface of the fin 5 and the gate electrode 6. By forming such a structure, channels are formed in both side surfaces of the fin 5, to realize a double gate structure. Such a FinFET is called as a double-gate type FinFET.
Besides a double-gate type FinFET, a triple-gate type FinFET is also known, in which a channel is formed in the upper side of the fin 5 as shown in FIG. 30 (Non-patent reference 2: 2003 Symposium on VLSI Technology Digest of Technical Papers, 2003, pp. 133-134). A triple-gate type FinFET is different from a double type FinFET in that a gate insulating film 7 is formed instead of a hard mask 9 in the upper side of the fin 5 under the gate electrode 6.
Meanwhile, for an existing bulk MOS device, a strained Si technique has been investigated for improving channel mobility and increasing a channel speed to improve an ON current while a supply voltage is reduced. In this technique, a Si lattice spacing is changed by applying stress to Si in a channel, to modulate a Si band structure. As a result, in a Si conduction band, degeneracy is broken to increase an electron occupancy of a double degeneracy valley with a light effective mass and interband scattering between a double degeneracy valley and a quadruple degeneracy valley is inhibited, resulting in improvement in mobility. In a valence band, it is believed that mobility is improved by breaking of degeneracy, inhibition of interband scattering between a light hole band and a heavy hole band and reduction in an effective mass.
Strain Si techniques can be generally classified into two types, depending on the way of applying strain to a channel Si.
A first method involves epitaxial growth of a Si layer on a relaxed SiGe layer (FIG. 1 in Non-patent reference 3; Applied Physics, The Japan Society of Applied Physics, Vol. 72 (3), 2003, pp. 220-290). First, as shown in FIG. 31, on a Si substrate 1 are sequentially formed a gradient type SiGe buffer 17 and a lattice-relaxed SiGe 18. In the gradient type SiGe buffer 17, a composition ratio X of Ge in SiGe is increased from 0% to x % (x is generally about from 10 to 30 or 40) toward the upper surface of the substrate. In the lattice-relaxed SiGe 18, SiGe is grown to relax a lattice while maintaining a high composition ratio X of Ge in SiGe. Since a lattice constant of Ge is larger than that of Si, lattice-relaxed SiGe has a larger lattice constant than that of Si. Therefore, a Si layer grown on a lattice-relaxed SiGe 18 such that the lattice matching occurs, has a larger lattice constant than that of a bulk Si and thus becomes a strained Si 19. When manufacturing a MOS type FET using such a strained Si layer as shown in FIG. 31, strain introduced in a channel improves mobility.
As shown FIG. 32, there is another method in which on a buried oxide film 2 is formed a lattice-relaxed SiGe 18 to form a SGOI (SiGe on Insulator) structure, on which a Si layer is grown to give a strained Si 19 (FIG. 3 in Non-patent reference 3).
Previous experimental results for a (100) plane have shown that a substrate Ge concentration x=25% (corresponding to about 1% strain) improves mobility by about 60 to 80% for electrons and about 20 to 50% for holes (FIG. 2 in Non-patent reference 3).
However, a relaxed SiGe layer giving strain to a channel Si layer has many dislocations and defects, so that it transfers dislocations and defects to the channel Si layer, leading to tendency to ingenerate dislocations and defects in the channel Si layer. Thus, when using the first method, a single MOS transistor may operate while it is difficult to operate an integrated circuit. Even if the integrated circuit operates, it is difficult to ensure a process yield.
The second method involves utilization of process strain. As process strain, strain generated by a capping layer or an STI (Shallow Trench Isolation) and so on can be used (Non-patent reference 4: International Electron Device Meeting Technical Digest, 2001, pp. 433-436). For example, as shown in FIG. 33, a nitride film is used as a capping layer 20 and a tension of the nitride film is utilized to apply strain to Si in a channel.
However, in the second method, strain is hard to be directly applied to a channel and it is difficult to control the amount of strain. It is because a capping layer or STI giving strain is distant from a channel region and thus strain is applied to the channel region via another substance.